The present invention relates to a semiconductor memory device; and more particular, to a semiconductor memory device, such as a Dynamic Random Access Memory (DRAM), to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out.
A DRAM cell is comprised of a switching transistor and a capacitor to store electric charges (data). The identification of the ‘High’ and ‘Low’ data is dependent upon a voltage applied to the capacitor, that is, dependent upon the presence or absence of the charges in the capacitor of the cell.
The data storage itself does not cause the power consumption mainly because the charges are stored in the capacitor. However, since a leakage current is caused in a PN junction of a MOS transistor, an initial amount of charges can disappear and this disappearance of the charges makes the data extinguished. To prevent this problem, before the data are extinguished, a recharge operation is performed in which the stored data is read out and the read-out data is restored.
The data maintenance is achieved by the above-mentioned recharge operation and this recharge operation is called a refresh operation. The refresh operation is typically carried out through a DRAM controller. The refresh is classified into two methods. The first method is an external refresh to issue a refresh command from the DRAM controller and the second method is a self refresh in which the DRAM controller issues only a refresh start signal and a refresh operation is continuously carried out itself until a refresh exit signal is issued.
FIG. 1 is a timing diagram illustrating an entry and an exit of a conventional self refresh mode. Referring to FIG. 1, the self refresh mode entry and exist of the conventional synchronization DRAM is recommended by JEDEC (Joint Electron Device Engineering Council) to execute the semiconductor standardization. When a clock enable signal CKE is in a low level and an auto refresh command (AREF: Auto REfresh) is inputted at a rising edge of the first external clock signal CLK after the logically low signal of the clock enable signal CKE ({circle around (1)}), the self refresh mode entry starts at the time of activating a self refresh enable signal (SREF_EN(Internal)) ({circle around (2)}). In the self refresh, restore operations associated with a specific group of cells are carried out using row address signals generated by a counter provided in the DRAM and other cell groups are restored by changing output signals of the counter for a predetermined period provided by an inner timer. When the external clock signal CLK is changed to a logic high level during this self refresh ({circle around (3)}) and a self refresh exit command (SREF: Self REfresh Exit) is inputted at a rising edge of the first external clock signal CLK after the logically high signal of the clock enable signal CKE, the self refresh enable signal (SREF_EN(Internal) is de-activated so that the self refresh mode is terminated ({circle around (4)}).
As illustrated above, the operation of the self refresh mode entry and exit is decided by the external clock signal (CLK) and the auto refresh command (AREF). In the meantime, the self refresh mode entry starts with the proper combination of the clock enable signal (CKE) and the auto refresh command (AREF) which are synchronized with the clock signal (CLK). However, if this combination has a problem such as an error or margin, an erroneous operation can be generated. Furthermore, there are many problems in circuit design, that is, there is a high probability of an error of the activation of the internal clock signal CLK after the clock enable signal CKE goes to a logic high level because the input of the external clock signal CLK is not valid while the self refresh operation is executed even though the self refresh mode is in the exit mode.